Wafer-scale integration

    flowchart
    AA["Associated Authors (0)"]
    C[Wafer-scale integration]
    BC["Broader Concepts (2)"]
    NC["Narrower Concepts (0)"]
    C== skos:broader ==>BC
    NC== skos:broader ==>C
    AA== dcterms:relation ==>C
    click BC "#broader-concepts"
    click NC "#narrower-concepts"
    click AA "#associated-authors"

    NI["add incoming edge"]
    NO["add outgoing edge"]
    NI-- ? -->C
    C-- ? -->NO
    click NI "#add-incoming-edge"
    click NO "#add-outgoing-edge"
    style NI stroke-width:2px,stroke-dasharray: 5 5
    style NO stroke-width:2px,stroke-dasharray: 5 5

Graph neighborhood for 'Wafer-scale integration'. Click aggregate nodes to navigate.

Wikidata: https://www.wikidata.org/wiki/Q7406100
OpenAlex ID: https://openalex.org/C2778638305 (API record)
OpenAlex Description: system of building very-large ined circuit networks that use an entire silicon wafer to produce a single "super-chip".
OpenAlex Level [?]: 3

Wafer-scale integration

Broader Concepts

Narrower Concepts

Associated Authors

Add Incoming Edge

Add Outgoing Edge