Clock skew
flowchart AA["Associated Authors (0)"] C[Clock skew] BC["Broader Concepts (1)"] NC["Narrower Concepts (8)"] C== skos:broader ==>BC NC== skos:broader ==>C AA== dcterms:relation ==>C click BC "#broader-concepts" click NC "#narrower-concepts" click AA "#associated-authors" NI["add incoming edge"] NO["add outgoing edge"] NI-- ? -->C C-- ? -->NO click NI "#add-incoming-edge" click NO "#add-outgoing-edge" style NI stroke-width:2px,stroke-dasharray: 5 5 style NO stroke-width:2px,stroke-dasharray: 5 5
- Wikidata
- https://www.wikidata.org/wiki/Q4382014
- OpenAlex ID
- https://openalex.org/C60501442 (API record)
- OpenAlex Description
- phenomenon of a synchronous digital circuit's clock signal arriving over multiple paths at different times
- OpenAlex Level [?]
- 4
Broader Concepts
Narrower Concepts
- CPU multiplier
- Clock drift
- Clock gating
- Clock network
- Digital clock manager
- Self-clocking signal
- Timing failure
- Vector clock
Associated Authors
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